// (C) Copyright 2012 Kystar. All rights reserved.

`timescale 1ns/100ps
`default_nettype none

module conv_444_to_422 
(
    input  wire          I_clk,
    input  wire          I_new_frame,
    input  wire [ 23: 0] I_data,
    input  wire          I_data_valid,
    output reg  [ 31: 0] O_data,
    output reg           O_data_valid
);

/******************************************************************************
                                <localparams>
******************************************************************************/

/******************************************************************************
                              <internal signals>
******************************************************************************/
reg  phase;
reg  [ 7: 0] last_data_8bit;

/******************************************************************************
                                <module body>
******************************************************************************/
always @(posedge I_clk)
    if (I_new_frame)
        phase <= 1'b0;
    else if (I_data_valid)
        phase <= ~phase;

always @(posedge I_clk)
    if (I_data_valid)
        last_data_8bit <= I_data[7:0];

always @(posedge I_clk)
    if (I_data_valid)
        begin
        if (phase == 1'b0)
            O_data <= {I_data[23:16], last_data_8bit, I_data[23:16], I_data[15:8]};
        else
            O_data <= {I_data[23:16], last_data_8bit, O_data[15:0]};
        end

always @(posedge I_clk)
    O_data_valid <= I_data_valid && (phase == 1'b1);

endmodule
`default_nettype wire

